Description: /* This program generates the DApkg.vhd file that is used to define
* the DA filter core and gives its parameters and the contents of the
* Distributed Arithmetic Look-up-table \"DALUT\" according to the DA algorithm-/ * This program generates the DApkg.vhd fi le that is used to define the DA * filter core and g ives its parameters and the contents of the Dis * tributed Arithmetic Look-up-table "DALUT" ac cording to the DA algorithm Platform: |
Size: 15595 |
Author:陈朋 |
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Description: 这是06年4月刚刚完成的程序，从opencore.org下载而来。用vhdl语言描写，以及matlab仿真，testbench，以及在xinlinx上的综合。
The MDCT core is two dimensional discrete cosine transform implementation designed for use in compression systems like JPEG. Architecture is based on parallel distributed arithmetic with butterfly computation.
-This is April 06 had just completed the process, from opencore.org downloaded from. Vhdl description language used, and Matlab simulation, testbench, and the Comprehensive xinlinx. The MDCT core is two dimensional discrete cosin e transform implementation designed for use in JPEG compression systems like. Architecture i 's based on parallel distributed arithmetic wit h butterfly computation. Platform: |
Size: 1767014 |
Author:陈朋 |
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Description: /* This program generates the DApkg.vhd file that is used to define
* the DA filter core and gives its parameters and the contents of the
* Distributed Arithmetic Look-up-table "DALUT" according to the DA algorithm-/* This program generates the DApkg.vhd fi le that is used to define the DA* filter core and g ives its parameters and the contents of the Dis* tributed Arithmetic Look-up-table "DALUT" ac cording to the DA algorithm Platform: |
Size: 15360 |
Author:陈朋 |
Hits:
Description: 这是06年4月刚刚完成的程序，从opencore.org下载而来。用vhdl语言描写，以及matlab仿真，testbench，以及在xinlinx上的综合。
The MDCT core is two dimensional discrete cosine transform implementation designed for use in compression systems like JPEG. Architecture is based on parallel distributed arithmetic with butterfly computation.
-This is April 06 had just completed the process, from opencore.org downloaded from. Vhdl description language used, and Matlab simulation, testbench, and the Comprehensive xinlinx. The MDCT core is two dimensional discrete cosin e transform implementation designed for use in JPEG compression systems like. Architecture i 's based on parallel distributed arithmetic wit h butterfly computation. Platform: |
Size: 1767424 |
Author:陈朋 |
Hits:
Description: A back-end implemenation of arithmetic coding for JPEG as defined in the standard. It is distributed as an add-on that can be used with the Independent JPEG groups library. The work of Guido Vollbeding.-A back-end co implemenation of arithmetic ding for JPEG as defined in the standard. It is di stributed as an add-on that can be used with the I ndependent groups JPEG library. The work of Gui Vollbeding do. Platform: |
Size: 47104 |
Author:Foxxing |
Hits:
Description: [PDF]Applications of Distributed Arithmetic to
Digital Signal Processing: A Tutorial Review Platform: |
Size: 180224 |
Author:Victor |
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Description: simple example of how Distributed Arithmetic works-simple example of how Distributed Arithmetic works Platform: |
Size: 83968 |
Author:Ali |
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Description: Distributed arithmetic used for multiplier-less FIR filter implementation to reduce the computational complexity.
Platform: |
Size: 93184 |
Author:sakhi |
Hits:
Description: actelIP核 的fircore
Core Generator
– Executable File Outputs Run-Time Library (RTL)
Code and Testbench Based on Input Parameters
– Self-Checking – Executable Tests Generated
Output against Algorithm
• Distributed Arithmetic (DA) Algorithm
– Multiplier-Free Computation
– Low Cost
– Optimized for Actel FPGAs
• Folding Architecture to Minimize Design Size
– Serialized Computation when System Clock
Rate is Faster than the Data Sample Rate
• Efficient Structure Using Embedded RAMs
– Lookup Tables Utilize Embedded RAMs
• On-Chip DA Lookup Table Generator for FPGA
with Embedded RAMs
• Embedded RAMs Initialized as DA Lookup Table
• DA Lookup Table ROM Synthesis for FPGA without
Embedded RAMs
• Multiple DA lookup Tables to Split Large Number
of Taps
• Actel FPGA-Optimized RTL Code
• Supports 2 to 128 Taps
• 1- to 32-Bit Input Data and Coefficient Precision-actelIPcore fircore
Core Generator
– Executable File Outputs Run-Time Library (RTL)
Code and Testbench Based on Input Parameters
– Self-Checking – Executable Tests Generated
Output against Algorithm
• Distributed Arithmetic (DA) Algorithm
– Multiplier-Free Computation
– Low Cost
– Optimized for Actel FPGAs
• Folding Architecture to Minimize Design Size
– Serialized Computation when System Clock
Rate is Faster than the Data Sample Rate
• Efficient Structure Using Embedded RAMs
– Lookup Tables Utilize Embedded RAMs
• On-Chip DA Lookup Table Generator for FPGA
with Embedded RAMs
• Embedded RAMs Initialized as DA Lookup Table
• DA Lookup Table ROM Synthesis for FPGA without
Embedded RAMs
• Multiple DA lookup Tables to Split Large Number
of Taps
• Actel FPGA-Optimized RTL Code
• Supports 2 to 128 Taps
• 1- to 32-Bit Input Data and Coefficient Precision Platform: |
Size: 1051648 |
Author:睿宸 |
Hits:
Description: In this article, we have proposed the internal architecture of a dedicated hardware for 1D/2D convolution-based 9/7 and
5/3 DWT filters, exploiting bit-parallel ‘distributed arithmetic’ (DA) to reduce the computation time of our proposed DWT
design while retaining the area at a comparable level to other recent existing designs. Despite using memory extensive bitparallel DA, we have successfully achieved 90% reduction in the memory size than that of the other notable architectures.
Through our proposed architecture, both the 9/7 and 5/3 DWT filters can be realized with a selection input, mode. With
the introduction of DA, we have incorporated pipelining and parallelism into our proposed convolution-based 1D/2D DWT
architectures. We have reduced the area by 38.3% and memory requirement by 90% than that of the latest remarkable designs.
The critical-path delay of our design is almost 50% than that of the other latest designs. We have successfully applied our
prototype 2D design for real-time image decomposition. The quality of the architecture in case of real-time image decomposition is measured by ‘peak signal-to-noise ratio’ and ‘computation time’, where our proposed design outperforms other
similar kind of software- and hardware-based implementations. Platform: |
Size: 3442321 |
Author:nalevihtkas |
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